ports

lang/verilator

verilator-3.912 – very fast free Verilog HDL simulator

Description

Verilator is the fastest free Verilog HDL simulator, and beats most
commercial simulators. It compiles synthesizable Verilog (not test-bench
code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
or SystemC code. It is designed for large projects where fast simulation
performance is of primary concern, and is especially well suited to
generate executable models of CPUs for embedded software design teams.

WWW: https://www.veripool.org/wiki/verilator/Intro

Categories:
devel lang

Library dependencies

None

Build dependencies

Run dependencies

None